ASIC Engineer

Cisco is hiring an ASIC Engineer in Bangalore.

Responsibilities

We are looking for a talented and motivated Layout Engineer to join Cisco’s Client Optics Group (COG) Engineering Team. In this role, you will support the physical implementation of high-performance analog and mixed-signal circuits for next-generation 100G, 200G, and 400G per lambda optical interconnect solutions.

You will contribute to all phases of physical design—from concept through tapeout—primarily for block-level layouts while assisting with top-level integration. Working closely with circuit designers, packaging engineers, process teams, and product engineers, you will help develop robust, manufacturable layouts that meet performance, reliability, area, and schedule goals.

Specific responsibilities include:

• Support layout development and physical implementation of analog, mixed-signal circuits, high-speed interfaces (including SerDes and PAM4), and supporting digital blocks

• Participate in block-level floorplanning, placement, routing, and integration for complex mixed-signal ICs

• Collaborate with circuit designers to translate schematics and performance targets into optimized physical layouts

• Optimize layouts for electrical performance, matching, parasitics, signal/power integrity, thermal behavior, yield, and manufacturability

• Ensure compliance with all foundry design rules (DRC, LVS, ERC, density, EM/IR, and reliability requirements)

• Assist in integration across analog, digital, and high-speed domains, including support for top-level assembly of SerDes, PAM4 paths, clocking, and control logic

• Review post-layout extraction results and support simulation closure

• Follow best practices for symmetry, shielding, isolation, and signal integrity

• Partner with packaging and product teams on bump planning, pad ring, ESD structures, and package integration

• Identify and help resolve layout-related issues impacting performance, yield, or production readiness

• Participate in layout reviews and provide input on feasibility, tradeoffs, and tapeout risks

• Collaborate with CAD teams to improve layout flows, automation, and productivity

• Support tapeout readiness, including database checks and signoff

Requirements

• Bachelor’s degree in Electrical Engineering or related field (Master’s preferred)

• 4-6 years of experience in custom IC layout for analog, mixed-signal, and high-speed designs

• Solid technical skills with an interest in growing into layout leadership; strong foundation in matching, symmetry, shielding, parasitic control, thermal management, and signal integrity

• Good knowledge of device-level layout techniques (common-centroid, interdigitation, guard rings, isolation structures)

• Proficiency with industry-standard tools such as Cadence Virtuoso and Calibre (or equivalent)

• Understanding of DRC, LVS, ERC, parasitic extraction, EM/IR analysis, and physical signoff flows

• Familiarity with ASIC/SoC tapeout processes is preferred

• Experience with scripting (Python, Perl, or TCL) for layout automation is a plus

• Comfortable working in Linux environments

• Excellent analytical, problem-solving, communication, and teamwork skills

• Demonstrated ability to contribute effectively and grow as a technical leader in a fast-paced environment

• Ability to work as a team player with cross-functional teams spread across geo-locations.

• Bachelor’s or Master’s in Electrical Engineering or equivalent field

• 3+ years of layout design experience in analog, mixed-signal, or high-speed IC development

• Hands-on experience supporting block-level layout efforts through tapeout

• Strong skills in custom layout design, physical verification, and parasitic-aware implementation

About Cisco

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