ASIC Digital Design Engineer

Cisco is hiring an ASIC Digital Design Engineer in Pune.

Responsibilities

We are looking for a talented and experienced Digital Design Engineer to join the Silicon One Optics Group (S1O) Digital Design Team and drive the digital design and integration of Cisco’s silicon photonics integrated circuits for next generation 100G, 200G, and 400G per lambda solutions.

In this role, you will own RTL design, and subsystem integration of digital logic used in high-performance optical interconnect products. You will work closely with analog/mixed-signal designers, verification engineers, physical design, DFT, firmware, packaging, process, and product engineering teams to develop robust, high-quality, and manufacturable designs that meet performance, power, reliability, and production requirements.

With a strong understanding of digital systems, RTL development, mixed-signal integration, ASIC/SoC design flow, and implementation readiness, you will participate in all phases of digital design from concept through tapeout and production support. You will drive block-level digital development for control functions, interfaces, receive/transmit paths, and integrated high-speed interface circuitry within a silicon photonics module, CPO (Co-Packaged Optics) engine. Specific responsibilities include:

• Own the RTL design of complex digital blocks and subsystems.
• Drive RTL design and integration for control functions, high speed interfaces, and receive/transmit paths.
• Own and review RTL quality, ensuring best practices in coding style, reuse, maintainability, and design robustness.
• Document block-level and top-level design specifications, interface definitions, and implementation plans.
• Work across analog and digital interfaces to ensure seamless mixed-signal integration.
• Collaborate closely with verification teams to define test plans, review coverage, debug issues, and ensure design intent is fully verified.
• Support full-chip integration involving high-speed IPs such as D2D IP, SerDes XSR, and integrated drivers/TIA.
• Support synthesis, timing closure, power optimization, low-power intent, and design-for-test (DFT) considerations.
• Develop scripts and automation flows for analysis, design checks, QoR tracking, and reporting using Python, Perl, Tcl, Shell, or C.
• Independently debug simulation and integration issues and identify root causes of design bugs.
• Support firmware/C coding activities related to CPU subsystem functionality and integration, where needed.
• Contribute to FPGA prototyping and validation activities where applicable.

Requirements

• Bachelor’s degree in Electrical Engineering or related field; Master’s degree preferred.

• Strong technical leader with 6-8 years of hands-on experience in digital design, RTL development, and ASIC/SoC integration.

• Strong understanding of digital architecture, finite state machines, control logic, datapath design, and interface design.

• Familiarity with protocols such as SPI, I2C, APB, AXI, or similar interfaces.

• Experience supporting block-to-chip integration.

• Strong knowledge of ASIC/SoC design flow, including RTL development, simulation, lint, CDC/RDC, synthesis, formal/equivalence checking, DFT, and implementation handoff.

• Experience with low-power design methodologies such as UPF/CPF.

• FPGA experience is a plus.

• Experience supporting lab bring-up, post-silicon validation, or ATE enablement is a plus.

• Strong analytical, problem-solving, teamwork and debugging skills.

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• 3+ years of digital design or ASIC/SoC RTL design experience, with demonstrated technical leadership in block or subsystem development.
• Strong skills in RTL design, digital integration, ASIC design flow, and DFT.
• Proficiency in Verilog/SystemVerilog.

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